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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input ? 0.5V to 2.75V Output
Data Sheet
R/W -1
DCL5
Bit 7
R/W -1
DCL4
R/W -1
DCL3
R/W -0
DCL2
R/W -1
DCL1
R/W -0
DCL0
R/W-0
HI
R/W-0
LO
Bit 0
The transfer function of the POL converter is shown
in Figure 44. It is a third order function with two
zeros and three poles. Pole 1 is the integrator pole,
Bit 7:2 DCL[5:0] , Duty Cycle Limitation
00h: 0
01h: 1/192
…
3Fh: 63/192
Bit 1: HI , ADC high saturation feed -forward
0: disabled
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Pole 2 is used in conjunction with Zero 1 and Zero 2
to adjust the phase lead and limit the gain increase
in mid band. Pole 3 is used as a high frequency low-
pass filter to limit PWM noise.
Bit 0:
1: enabled
LO , ADC low saturation feed -forward
Magnitude[dB]
0: disabled
50
Z1
P1 Z2
P2
P3
1: enabled
40
P1: Pole 1
P2: Pole 3
P3: Pole 3
Figure 43. Duty Cycle Limit Register
8.4.4 ADC Saturation Feedforward
To speed up the PWM response in case of heavy
30
20
10
Z1: Zero 1
Z2: Zero 2
Freq
dynamic loads, the duty cycle can be forced either to
0.1
1
10
100
1000
[kHz]
0 or the duty cycle limit depending on the polarity of
the transient. This function is equivalent to having
Phase
[°]
+45
two comparators defining a window around the
output voltage setpoint. When an error signal is
inside the window, it will produce gradual duty cycle
0
-45
0.1
1
10
100
1000
Freq
[kHz]
change proportional to the error signal. If the error
signal goes outside the window (usually due to large
-90
-135
output current steps), the duty cycle will change to its
limit in one switching cycle. In most cases this will
significantly improve transient response of the
-180
Figure 44. Transfer Function of PWM
controller, reducing amount of required external
capacitance.
Under certain circumstances, usually when the
maximum duty cycle limit significantly exceeds its
nominal value, the ADC saturation can lead to the
overcompensation of the output error. The
phenomenon manifests itself as low frequency
oscillations on the output of the POL. It can usually
be reduced or eliminated by disabling the ADC
Positions of poles and zeroes are determined by
coefficients of the digital filter. The filter is
characterized by four numerator coefficients ( C 0 , C 1 ,
C 2 , C 3 ) and three denominator coefficients ( B 1 , B 2 ,
B 3 ). The coefficients are automatically calculated
when desired frequency of poles and zeros is
entered in the GUI PWM Controller window. The
coefficients are stored in the C0H, C0L, C1H, C1L,
C2H, C2L, C3H, C3L, B1, B2, and B3 registers.
saturation or limiting the maximum duty cycle to 120-
140% of the calculated value. It is not recommended
to use ADC saturation for output voltages higher
than 2.0V.
Note :
The GUI automatically transforms zero and pole
frequencies into the digital filter coefficients. It is strongly
recommended to use the GUI to determine the filter
coefficients.
The ADC saturation feedforward can be
programmed in the GUI PWM Controller window or
directly via the I 2 C bus by writing into the DCL
register.
Programming feedback loop compensation allows
optimizing POL performance for various application
conditions. For example, increase in bandwidth can
significantly improve dynamic response.
8.4.5 Feedback Loop Compensation
8.5
Current Share
Feedback loop compensation can be programmed in
the GUI PWM Controller window by setting
frequency of poles and zeros of the transfer function.
The POL converters are equipped with the digital
current share function. To activate the current share,
interconnect the CS pins of the POLs connected in
ZD-01674 Rev. 1.2, 02-Jul-10
www.power-one.com
Page 25 of 30
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